RISC-V /Debug /Trigger Info (32-bit tinfo)

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Interpret as Trigger Info (32-bit tinfo)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0info0 (0)version

version=0

Description

This register provides access to the trigger selected by {csr-tselect}. The reset values listed here apply to every underlying trigger.

This register is optional if no triggers are implemented, or if {tdata1-type} is not writable and {tinfo-version} would be 0. In this case the debugger can read the only supported type from {csr-tdata1}.

Fields

info

One bit for each possible {tdata1-type} enumerated in {csr-tdata1}. Bit N corresponds to type N. If the bit is set, then that type is supported by the currently selected trigger.

If the currently selected trigger doesn’t exist, this field contains 1.

version

Contains the version of the Sdtrig extension implemented.

0 (0): Supports triggers as described in this spec at commit 5a5c078, made on February 2, 2023.

In these older versions:

  1. {csr-mcontrol6} has a timing bit identical to {mcontrol-timing}
  2. {mcontrol6-hit0} behaves just as {mcontrol-hit}.
  3. {mcontrol6-hit1} is read-only 0.
  4. Encodings for {mcontrol6-size} for access sizes larger than 64 bits are different.

1 (1): Supports triggers as described in the ratified version 1.0 of this document.

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